module tb_mux2_1;
	
	reg InA;
	reg InB;
	reg S;
	wire Out;

	//Module instantiation
	mux2_1 DUB(.InA(InA), .InB(InB), .S(S), .Out(Out));

	initial
	begin 
	  S= 1'b0;

	  InA = 1'b0;
	  InB = 1'b0;

          #10 InA = 1'b1;
	      InB = 1'b0;

          #10 InA = 1'b0;
	      InB = 1'b1;
	  
          #10 InA = 1'b1;
	      InB = 1'b1;

          #10 S = 1'b1;
	      InA = 1'b0;
	      InB = 1'b0;

          #10 InA = 1'b1;
	      InB = 1'b0;

          #10 InA = 1'b0;
	      InB = 1'b1;
	  
          #10 InA = 1'b1;
	      InB = 1'b1;


          #10 $finish;
	  end

     always@(S, InA, InB, Out)
	begin
             #5
	     case(S)
		0'b0 : $display("Expecting InA : %b, Got %b", InA, Out);
		1'b1 : $display("Expecting InB : %b, Got %b", InB, Out);
	     endcase
	 end
endmodule
